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1024-/256-position, 1% resistor tolerance error, i 2 c interface and 50-tp memory digital rheostat ad5272/ad5274 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009C2010 analog devices, inc. all rights reserved. features single-channel, 1024-/256-position resolution 20 k, 50 k, 100 k nominal resistance maximum 1% nominal resistor tolerance error 50-times programmable (50-tp) wiper memory rheostat mode temperature coefficient: 5 ppm/c 2.7 v to 5.5 v single-supply operation 2.5 v to 2.75 v dual-supply operation for ac or bipolar operations i 2 c-compatible interface wiper setting readback power on refreshed from 50-tp memory thin lfcsp 10-lead, 3 mm 3 mm 0.8 mm package compact msop, 10-lead 3 mm 4.9 mm 1.1 mm package applications mechanical rheostat replacements op-amp: variable gain control instrumentation: gain, offset adjustment programmable voltage to current conversions programmable filters, delays, time constants programmable power supply sensor calibration functional block diagram 10/8 v dd a w ad5272/ad5274 scl addr sda i 2 c serial interface power-on reset rdac register 50-tp memory block reset v ss ext_cap gnd 08076-001 figure 1. general description the ad5272/ad5274 1 are single-channel, 1024-/256-position digital rheostats that combine industry leading variable resistor performance with nonvolatile memory (nvm) in a compact package. the ad5272/ad5274 ensure less than 1% end-to-end resistor tolerance error and offer 50-times programmable (50-tp) memory. the guaranteed industry leading low resistor tolerance error feature simplifies open-loop applications as well as precision calibration and tolerance matching applications. the ad5272/ad5274 device wiper settings are controllable through the i 2 c-compatible digital interface. unlimited adjustments are allowed before programming the resistance value into the 50-tp memory. the ad5272/ad5274 do not require any external voltage supply to facilitate fuse blow and there are 50 opportunities for permanent programming. during 50-tp activation, a permanent blow fuse command freezes the wiper position (analogous to placing epoxy on a mechanical trimmer). the ad5272/ad5274 are available in a 3 mm 3 mm 10-lead lfcsp package and in a 10-lead msop package. the parts are guaranteed to operate over the extended industrial temperature range of ?40c to +125c. 1 protected by u.s. patent number 7688240 .;
ad5272/ad5274 rev. c | page 2 of 28 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? electrical characteristicsad5272 .......................................... 3 ? electrical characteristicsad5274 .......................................... 5 ? interface timing specifications.................................................. 7 ? absolute maximum ratings............................................................ 9 ? thermal resistance ...................................................................... 9 ? esd caution.................................................................................. 9 ? pin configuration and function descriptions........................... 10 ? typical performance characteristics ........................................... 11 ? test circuits..................................................................................... 17 ? theory of operation ...................................................................... 18 ? serial data interface................................................................... 18 ? shift register ............................................................................... 18 ? write operation.......................................................................... 19 ? read operation........................................................................... 20 ? rdac register............................................................................ 21 ? 50-tp memory block ................................................................ 21 ? write protection ......................................................................... 21 ? 50-tp memory write-acknowledge polling.......................... 23 ? reset ............................................................................................. 23 ? resistor performance mode...................................................... 23 ? shutdown mode ......................................................................... 23 ? rdac architecture.................................................................... 23 ? programming the variable resistor......................................... 23 ? ext_cap capacitor.................................................................. 24 ? terminal voltage operating range ......................................... 24 ? power-up sequence ................................................................... 24 ? outline dimensions ....................................................................... 25 ? ordering guide .......................................................................... 26 ? revision history 11/10rev. b to rev. c changes to figure 24...................................................................... 14 5/10rev. a to rev. b added lfcsp package.................................................. throughout changed otp to 50-tp ................................................ throughout changes to features section and applications section............... 1 added endnote 1 .............................................................................. 1 changes to table 1............................................................................ 3 added table 3.................................................................................... 4 changes to table 4............................................................................ 5 added table 6.................................................................................... 6 changes to table 8 and table 9....................................................... 9 added figure 5................................................................................ 10 added exposed pad note to table 10.......................................... 10 changes to typical performance characteristics....................... 11 changes to resistor performance mode section ....................... 23 updated outline dimensions ....................................................... 25 changes to ordering guide .......................................................... 26 3/10rev. 0 to rev. a changes to product title and general description section....... 1 changes to theory of operation section.................................... 15 10/09revision 0: initial version
ad5272/ad5274 rev. c | page 3 of 28 specifications electrical characteristicsad5272 v dd = 2.7 v to 5.5 v, v ss = 0 v; v dd = 2.5 v to 2.75 v, v ss = ?2.5 v to ?2.75 v; ?40c < t a < +125c, unless otherwise noted. table 1. parameter symbol test conditions/comments min typ 1 max unit dc characteristicsrheostat mode resolution 10 bits resistor integral nonlinearity 2 , 3 r-inl r aw = 20 k, |v dd ? v ss | = 3.0 v to 5.5 v ?1 +1 lsb r aw = 20 k, |v dd ? v ss | = 2.7 v to 3.0 v ?1 +1.5 lsb r aw = 50 k, 100 k ?1 +1 lsb resistor differential nonlinearity 2 r-dnl ?1 +1 lsb nominal resistor tolerance r-perf mode 4 see table 2 and table 3 ?1 0.5 +1 % normal mode 15 % resistance temperature coefficient 5 , 6 code = full scale 5 ppm/c wiper resistance code = zero scale 35 70 resistor terminals terminal voltage range 5 , 7 v ss v dd v capacitance 5 a f = 1 mhz, measured to gnd, code = half scale 90 pf capacitance 5 w f = 1 mhz, measured to gnd, code = half scale 40 pf common-mode leakage current 5 v a = v w 50 na digital inputs input logic 5 high v inh 2.0 v low v inl 0.8 v input current i in 1 a input capacitance 5 c in 5 pf digital output output voltage 5 high v oh r pull_up = 2.2 k to v dd v dd ? 0.1 v low v ol r pull_up = 2.2 k to v dd v dd = 2.7 v to 5.5 v, v ss = 0 v 0.4 v v dd = 2.5 v to 2.75 v, v ss = ?2.5 v to ?2.75 v 0.6 v tristate leakage current ?1 +1 a output capacitance 5 5 pf power supplies single-supply power range v ss = 0 v 2.7 5.5 v dual-supply power range 2.5 2.75 v supply current positive i dd 1 a negative i ss ?1 a 50-tp store current 5 , 8 positive i dd_otp_store 4 ma negative i ss_otp_store ?4 ma 50-tp read current 5 , 9 positive i dd_otp_read 500 a negative i ss_otp_read ?500 a power dissipation 10 v ih = v dd or v il = gnd 5.5 w
ad5272/ad5274 rev. c | page 4 of 28 parameter symbol test conditions/comments min typ 1 max unit power supply rejection ratio 5 psrr v dd /v ss = 5 v 10% db r aw = 20 k ?66 ?55 r aw = 50 k ?75 ?67 r aw = 100 k ?78 ?70 dynamic characteristics 5 , 11 bandwidth ?3 db, r aw = 10 k, terminal w, see figure 41 khz r aw = 20 k 300 r aw = 50 k 120 r aw = 100 k 60 total harmonic distortion v a = 1 v rms, f = 1 khz, code = half scale db r aw = 20 k ?90 r aw = 50 k ?88 r aw = 100 k ?85 resistor noise density code = half scale, t a = 25c, f = 10 khz nv/hz r aw = 20 k 50 r aw = 50 k 25 r aw = 100 k 32 1 typical specifications represe nt average readings at 25c, v dd = 5 v, and v ss = 0 v. 2 resistor position nonlinearity error (r-inl) is the deviatio n from an ideal value measured be tween the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. 3 the maximum current in each code is defined by i aw = (v dd ? 1)/r aw . 4 the terms, resistor performance mode and r-perf mode, are used interchangeably. see the resistor performance mode section. 5 guaranteed by design and not subject to production test. 6 see figure 24 for more details. 7 resistor terminal a and resistor terminal w have no limitations on polarity with re spect to each other. dual-supply operation enables ground referenced bipolar signal adjustment. 8 different from operating current, the supply curre nt for the fuse program lasts approximately 55 ms. 9 different from operating current, the supply curr ent for the fuse read lasts approximately 500 ns. 10 p diss is calculated from (i dd v dd ) + (i ss v ss ). 11 all dynamic characteristics use v dd = +2.5 v, v ss = ?2.5 v. table 2. ad5272 resistor pe rformance mode code range resistor tolerance per code |v dd ? v ss | = 4.5 v to 5.5 v |v dd ? v ss | = 2.7 v to 4.5 v r-tolerance 1% r-tolerance from 0x078 to 0x3ff from 0x0be to 0x3ff 2% r-tolerance from 0x037 to 0x3ff from 0x055 to 0x3ff 3% r-tolerance from 0x028 to 0x3ff from 0x037 to 0x3ff table 3. ad5272 50 k and 100 k resi stor performance mode code range resistor tolerance per code r aw = 50 k r aw = 100 k r-tolerance 1% r-tolerance from 0x078 to 0x3ff from 0x04b to 0x3ff 2% r-tolerance from 0x055 to 0x3ff from 0x032 to 0x3ff 3% r-tolerance from 0x032 to 0x3ff from 0x019 to 0x3ff
ad5272/ad5274 rev. c | page 5 of 28 electrical characteristicsad5274 v dd = 2.7 v to 5.5 v, v ss = 0 v; v dd = 2.5 v to 2.75 v, v ss = ?2.5 v to ?2.75 v; ?40c < t a < +125c, unless otherwise noted. table 4. parameter symbol test conditions/comments min typ 1 max unit dc characteristics rheostat mode resolution 8 bits resistor integral nonlinearity 2 , 3 r-inl ?1 +1 lsb resistor differential nonlinearity 2 r-dnl ?1 +1 lsb nominal resistor tolerance r-perf mode 4 see table 5 and table 6 ?1 0.5 +1 % normal mode 15 % resistance temperature coefficient 5 , 6 code = full scale 5 ppm/c wiper resistance code = zero scale 35 70 resistor terminals terminal voltage range 5 , 7 v ss v dd v capacitance 5 a f = 1 mhz, measured to gnd, code = half scale 90 pf capacitance 5 w f = 1 mhz, measured to gnd, code = half scale 40 pf common-mode leakage current 5 v a = v w 50 na digital inputs input logic 5 high v inh 2.0 v low v inl 0.8 v input current i in 1 a input capacitance 5 c in 5 pf digital output output voltage 5 high v oh r pull_up = 2.2 k to v dd v dd ? 0.1 v low v ol r pull_up = 2.2 k to v dd v dd = 2.7 v to 5.5 v, v ss = 0 v 0.4 v v dd = 2.5 v to 2.75 v, v ss = ?2.5 v to ?2.75 v 0.6 v tristate leakage current ?1 +1 a output capacitance 5 5 pf power supplies single-supply power range v ss = 0 v 2.7 5.5 v dual-supply power range 2.5 2.75 v supply current positive i dd 1 a negative i ss ?1 a otp store current 5 , 8 positive i dd_otp_store 4 ma negative i ss_otp_store ?4 ma otp read current 5 , 9 positive i dd_otp_read 500 a negative i ss_otp_read ?500 a power dissipation 10 v ih = v dd or v il = gnd 5.5 w power supply rejection ratio 5 psrr v dd /v ss = 5 v 10% db r aw = 20 k ?66 ?55 r aw = 50 k ?75 ?67 r aw = 100 k ?78 ?70
ad5272/ad5274 rev. c | page 6 of 28 parameter symbol test conditions/comments min typ 1 max unit dynamic characteristics 5 , 11 bandwidth ?3 db, r aw = 10 k, terminal w, see figure 41 khz r aw = 20 k 300 r aw = 50 k 120 r aw = 100 k 60 total harmonic distortion v a = 1 v rms, f = 1 khz, code = half scale db r aw = 20 k ?90 r aw = 50 k ?88 r aw = 100 k ?85 resistor noise density code = half scale, t a = 25c, f = 10 khz nv/hz r aw = 20 k 50 r aw = 50 k 25 r aw = 100 k 32 1 typical specifications represe nt average readings at 25c, v dd = 5 v, and v ss = 0 v. 2 resistor position nonlinearity error (r-inl) is the deviatio n from an ideal value measured be tween the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. 3 the maximum current in each code is defined by iaw = (v dd ? 1)/r aw . 4 the terms, resistor performance mode and r-perf mode, are used interchangeably. see the resistor performance mode section. 5 guaranteed by design and not subject to production test. 6 see figure 24 for more details. 7 resistor terminal a and resistor terminal w have no limitations on polarity with re spect to each other. dual-supply operation enables ground referenced bipolar signal adjustment. 8 different from operating current, the supply curre nt for the fuse program lasts approximately 55 ms. 9 different from operating current, the supply curr ent for the fuse read lasts approximately 500 ns. 10 p diss is calculated from (i dd v dd ) + (i ss v ss ). 11 all dynamic characteristics use v dd = +2.5 v, v ss = ?2.5 v. table 5. ad5274 resistor pe rformance mode code range resistor tolerance per code |v dd ? v ss | = 4.5 v to 5.5 v |v dd ? v ss | = 2.7 v to 4.5 v r-tolerance 1% r-tolerance from 0x1e to 0xff from 0x32 to 0xff 2% r-tolerance from 0x0f to 0xff from 0x19 to 0xff 3% r-tolerance from 0x06 to 0xff from 0x0e to 0xff table 6. ad5274 50 k and 100 k resi stor performance mode code range resistor tolerance per code r aw = 50 k r aw = 100 k r-tolerance 1% r-tolerance from 0x1e to 0xff from 0x14 to 0xff 2% r-tolerance from 0x14 to 0xff from 0x0f to 0xff 3% r-tolerance from 0x0a to 0xff from 0x0a to 0xff
ad5272/ad5274 rev. c | page 7 of 28 interface timing specifications v dd = 2.5 v to 5.5 v; all specifications t min to t max , unless otherwise noted. table 7. limit at t min , t max parameter conditions 1 min max unit description f scl 2 standard mode 100 khz serial clock frequency fast mode 400 khz serial clock frequency t 1 standard mode 4 s t high , scl high time fast mode 0.6 s t high , scl high time t 2 standard mode 4.7 s t low , scl low time fast mode 1.3 s t low , scl low time t 3 standard mode 250 ns t su;dat , data setup time fast mode 100 ns t su;dat , data setup time t 4 standard mode 0 3.45 s t hd;dat , data hold time fast mode 0 0.9 s t hd;dat , data hold time t 5 standard mode 4.7 s t su;sta , set-up time for a repeated start condition fast mode 0.6 s t su;sta , set-up time for a repeated start condition t 6 standard mode 4 s t hd;sta , hold time (repeated) start condition fast mode 0.6 s t hd;sta , hold time (repeated) start condition high speed mode 160 ns t hd;sta , hold time (repeated) start condition t 7 standard mode 4.7 s t buf , bus free time between a stop and a start condition fast mode 1.3 s t buf , bus free time between a stop and a start condition t 8 standard mode 4 s t su;sto , setup time for a stop condition fast mode 0.6 s t su;sto , setup time for a stop condition t 9 standard mode 1000 ns t rda , rise time of sda signal fast mode 300 ns t rda , rise time of sda signal t 10 standard mode 300 ns t fda , fall time of sda signal fast mode 300 ns t fda , fall time of sda signal t 11 standard mode 1000 ns t rcl , rise time of scl signal fast mode 300 ns t rcl , rise time of scl signal t 11a standard mode 1000 ns t rcl1 , rise time of scl signal after a repeated start condition and after an acknowledge bit fast mode 300 ns t rcl1 , rise time of scl signal after a repeated start condition and after an acknowledge bit t 12 standard mode 300 ns t fcl , fall time of scl signal fast mode 300 ns t fcl , fall time of scl signal t 13 reset pulse time 20 ns minimum reset low time t sp 3 fast mode 0 50 ns pulse width of spike suppressed t exec 4 , 5 500 ns command execute time t rdac_r-perf 2 s rdac register write command execute time (r-perf mode) t rdac_normal 600 ns rdac register write co mmand execute time (normal mode) t memory_read 6 s memory readback execute time t memory_program 350 ms memory program time t reset 600 s reset 50-tp restore time t power-up 6 2 ms power-on 50-tp restore time 1 maximum bus capacitance is limited to 400 pf. 2 the sda and scl timing is measured with the input filters enabled. switching off the input filters improves the transfer rate but has a negative effect on emc behavior of the part. 3 input filtering on the scl and sda inputs suppress noise spikes that are less than 50 ns for fast mode. 4 refer to t rdac_r-perf and t rdac_normal for rdac register write operations. 5 refer to t memory_read and t memory_program for memory comma nds operations. 6 maximum time after v dd ? v ss is equal to 2.5 v.
ad5272/ad5274 rev. c | page 8 of 28 shift register and timing diagrams data bits db9 (msb) db0 (lsb) d7 d6 d5 d4 d3 d2 d1 d0 control bits c0 c1 c2 d9 d8 c3 0 0 08076-003 figure 2. shift register content 08076-002 reset t 7 t 6 t 2 t 4 t 11 t 12 t 6 t 5 t 10 t 1 scl sda ps s p t 3 t 8 t 9 t 1 3 figure 3. 2-wire serial interface timing diagram
ad5272/ad5274 rev. c | page 9 of 28 absolute maximum ratings t a = 25c, unless otherwise noted. table 8. parameter rating v dd to gnd C0.3 v to +7.0 v v ss to gnd +0.3 v to ?7.0 v v dd to v ss 7 v v a , v w to gnd v ss ? 0.3 v, v dd + 0.3 v digital input and output voltage to gnd ?0.3 v to v dd + 0.3 v ext_cap to v ss 7 v i a , i w continuous r aw = 20 k 3 ma r aw = 50 k, 100 k 2 ma pulsed 1 frequency > 10 khz mcc 2 /d 3 frequency 10 khz mcc 2 /d 3 operating temperature range 4 ?40c to +125c maximum junction temperature (t j maximum) 150c storage temperature range ?65c to +150c reflow soldering peak temperature 260c time at peak temperature 20 sec to 40 sec package power dissipation (t j max ? t a )/ ja stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is defined by jedec specification jesd-51 and the value is dependent on the test board and test environment. table 9. thermal resistance package type ja 1 jc unit 10-lead lfcsp 50 3 c/w 10-lead msop 135 n/a c/w 1 jedec 2s2p test board, still air (0 m/s air flow). esd caution 1 maximum terminal current is bounde d by the maximum current handling of the switches, maximum power dissip ation of the package, and maximum applied voltage across any two of the a and w terminals at a given resistance. 2 maximum continuous current 3 pulse duty factor. 4 includes program ming of 50-tp memory.
ad5272/ad5274 rev. c | page 10 of 28 pin configuration and fu nction descriptions 08076-004 addr v dd 1 v ss 2 a 3 w 4 reset 10 9 8 scl 7 5 ext_cap sda 6 gnd notes 1. the exposed pad is left floating or is tied to v ss . ad5272/ ad5274 (exposed pad) 08076-040 v dd 1 v ss 2 a 3 w 4 10 9 8 scl addr 7 5 ext_cap ad5272/ ad5274 top view (not to scale) sda 6 gnd reset figure 4. msop pin configuration figure 5. lfcsp pin configuration table 10. pin function descriptions pin o. mnemonic description 1 v dd positive power supply. decouple this pin with 0.1 f ceramic capacitors and 10 f capacitors. 2 a terminal a of rdac. v ss v a v dd . 3 w wiper terminal of rdac. v ss v w v dd . 4 v ss negative supply. connect to 0 v for single-supply applicat ions. decouple this pin with 0.1 f ceramic capacitors and 10 f capacitors. 5 ext_cap external capacitor. connect a 1 f capacitor between ext_cap and v ss . this capacitor must have a voltage rating of 7 v. 6 gnd ground pin, logic ground reference. 7 reset hardware reset pin. refreshes the rdac register with the contents of the 50-tp memory register. factory default loads midscale until the first 50-tp wiper memory location is programmed. reset is active low. tie reset to v dd if not used. 8 sda serial data line. this is used in conjunction with the scl line to clock data into or out of the 16-bit input registers. it is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor. 9 scl serial clock line. this is used in conjunction with the sd a line to clock data into or out of the 16-bit input registers. 10 addr tristate address input. sets th e two least significant bits (bit a1, bit a0) of the 7-bit slave address (see table 11 ). epad exposed pad (lfcsp only) leave floating or tie to v ss .
ad5272/ad5274 rev. c | page 11 of 28 typical performance characteristics ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 128 256 384 512 640 768 896 1023 inl (lsb) code (decimal) +125c +25c ?40c r aw = 20k ? dnl (lsb) 08076-010 figure 6. r-inl in r-perf mode vs. code vs. temperature (ad5272) code (decimal) 08076-011 ?0.6 ?0.5 0 128 256 384 512 640 768 896 1023 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 +25c ?40c +125c r aw = 20k ? figure 7. r-dnl in r-perf mode vs. code vs. temperature (ad5272) ?0.1 0 0.1 code (decimal) 0.4 0.2 0.3 0.5 inl (lsb) 0 128 256 384 512 640 768 896 1023 +125c +25c ?40c 08076-014 r aw = 20k ? figure 8. r-inl in normal mode vs. code vs. temperature (ad5272) 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 0 256 512 768 1023 code (decimal) inl (lsb) 08076-111 20k? 50k? 100k ? t a = 25c figure 9. r-inl in r-perf mode vs. code vs. nominal resistance (ad5272) 0 256 512 768 1023 code (decimal) 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 dnl (lsb) 08076-120 20k ? 50k? 100k ? t a = 25c figure 10. r-dnl in r-perf mode vs. code vs. nominal resistance (ad5272) 0 256 512 768 1023 code (decimal) 0.4 0.6 0.2 0 ?0.2 ?0.4 inl (lsb) 08076-121 20k? 50k? 100k ? t a = 25c figure 11. r-inl in normal mode vs. code vs. nominal resistance (ad5272)
ad5272/ad5274 rev. c | page 12 of 28 ?0.15 ?0.10 ?0.05 0.10 0 0.05 0.15 dnl (lsb) code (decimal) 0 128 256 384 512 640 768 896 1023 +125c +25c ?40c 08076-015 r aw = 20k ? figure 12. r-dnl in normal mode vs. code vs. temperature (ad5272) code (decimal) 0 64 128 192 255 ?0.10 ?0.05 0 0.15 0.05 0.10 0.20 inl (lsb) +125c +25c ?40c 08076-013 r aw = 20k ? figure 13. r-inl in r-perf mode vs. code vs. temperature (ad5274) ?0.14 ?0.12 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 dnl (lsb) code (decimal) +125c +25c ?40c 08076-012 r aw = 20k ? 0 64 128 192 255 figure 14. r-dnl in r-perf mode vs. code vs. temperature (ad5274) 0 256 512 768 1023 code (decimal) 0.15 0.10 0.05 0 ?0.10 ?0.05 ?0.15 ?0.20 dnl (lsb) 08076-122 20k ? 50k ? 100k ? t a = 25c figure 15. r-dnl in normal mode vs. code vs. nominal resistance (ad5272) code (decimal) 0 64 128 192 255 0.15 0.10 0.05 0 ?0.05 ?0.10 inl (lsb) 08076-123 20k ? 100k ? t a = 25c figure 16. r-inl in r-perf mode vs . code vs. nominal resistance (ad5274) code (decimal) 0 64 128 192 255 0.15 0.10 0.05 0 ?0.10 ?0.15 ?0.05 dnl (lsb) 08076-125 20k ? 100k ? t a = 25c figure 17. r-dnl in r-perf mode vs. code vs. nominal resistance (ad5274)
ad5272/ad5274 rev. c | page 13 of 28 code (decimal) 0 64 128 192 255 ?0.02 0 0.02 0.08 0.04 0.06 0.10 inl (lsb) +125c +25c ?40c 08076-016 r aw = 20k ? figure 18. r-inl in normal mode vs. code vs. temperature (ad5274) code (decimal) 0 64 128 192 255 ?0.03 ?0.02 ?0.01 0.02 0 0.01 0.03 dnl (lsb) +125c +25c ?40c 08076-017 r aw = 20k ? figure 19. r-dnl in normal mode vs. code vs. temperature (ad5274) ?500 ?400 ?300 ?200 ?100 0 100 200 300 400 500 current (na) temperature (c) ?40 ?30 ?20 ?10 0 20 30 40 50 60 70 80 90 100 110 10 i dd = 5v i ss = 5v i dd = 3v i ss = 3v 08076-018 figure 20. supply current (i dd , i ss ) vs. temperature code (decimal) 0 64 128 192 255 0.15 0.10 0.05 0 ?0.10 ?0.05 inl (lsb) 08076-126 20k? 100k ? t a = 25c figure 21. r-inl in normal mode vs. code vs. nominal resistance (ad5274) code (decimal) 0 64 128 192 255 0.010 0.008 0.006 0.004 0 ?0.002 0.002 dnl (lsb) 008076-027 20k ? 100k ? t a = 25c figure 22. r-dnl in normal mode vs. code vs. nominal resistance (ad5274) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 ?0.1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v logic (v) i dd (ma) 08076-110 figure 23. supply current (i dd ) vs. digital input voltage
ad5272/ad5274 rev. c | page 14 of 28 0 5 10 15 20 25 30 35 40 45 50 rheostat mode tempco (ppm/c) 0 256 512 768 1023 0 64 128 192 255 ad5272 ad5274 code (decimal) 08076-019 20k ? 50k ? 100k ? v dd /v ss = 5v/0v figure 24. tempco r wa /t vs. code ?60 ?50 ?40 ?10 ?30 ?20 0 1k 10k 100k 1m 10m gain (db) frequency (hz) 0x200 (0x80) 0x100 (0x40) 0x080 (0x20) 0x040 (0x10) 0x020 (0x08) 0x010 (0x04) 0x008 (0x02) 0x004 (0x01) 0x002 0x001 ad5272 (ad5274) 08076-031 figure 25. 20 k gain vs. code vs. frequency ?60 ?50 ?40 ?10 ?30 ?20 0 1k 10k 100k 1m 10m gain (db) frequency (hz) 0x200 (0x80) 0x100 (0x40) 0x080 (0x20) 0x040 (0x10) 0x020 (0x08) 0x010 (0x04) 0x008 (0x02) 0x004 (0x01) 0x002 0x001 ad5272 (ad5274) 08076-032 figure 26. 50 k gain vs. code vs. frequency 0 1 2 3 4 5 6 7 theoretical i wa_max (ma) code (decimal) 0 256 512 768 1023 0 64 128 192 255 ad5272 ad5274 v dd /v ss =5v/0v 08076-028 20k ? 50k ? 100k ? figure 27. theoretical maximum current vs. code ?60 ?70 ?50 ?40 ?10 ?30 ?20 0 1k 10k 100k 1m 10m gain (db) frequency (hz) 0x200 (0x80) 0x100 (0x40) 0x080 (0x20) 0x040 (0x10) 0x020 (0x08) 0x010 (0x04) 0x008 (0x02) 0x004 (0x01) 0x002 0x001 ad5272 (ad5274) 08076-041 figure 28. 100 k gain vs. code vs. frequency psrr (db) frequency (hz) 100 1k 10k 100k v dd /v ss = 5v/0v code = half scale 0 8076-024 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 50k ? 100k ? 20k ? figure 29. psrr vs. frequency
ad5272/ad5274 rev. c | page 15 of 28 0 ?20 ?40 ?60 ?100 ?80 100 08076-025 20k ? 50k ? 100k ? frequency (hz) 1k 10k 100k thd + n (db) v dd /v ss = 5v/0v code = half scale noise bw = 22khz v in = 1v rms figure 30. thd + n vs. frequency 0.03 0.01 0 0.02 ?0.01 ?0.02 ?0.04 ?0.03 ?1 4 9 14 19 time (s) voltage (v) 08076-043 20k ? 50k ? 100k ? figure 31. maximum glitch energy 45 35 30 40 25 20 0 15 10 5 2.7 3.2 3.7 4.2 4.7 5.2 20k? 50k? 100k? v dd (v) 08076-021 t a = 25c number of codes (ad5272) number of codes (ad5274) 7.50 8.75 6.25 5.00 3.75 2.50 1.25 0 11.25 10.00 figure 32. maximum code loss vs. temperature 0 ?20 ?30 ?10 ?40 ?50 ?100 ?60 ?70 ?80 ?90 0.001 0.01 0.1 1 20k? 50k? 100k ? 08076-026 voltage (v rms ) thd + n (db) v dd /v ss = 5v/0v code = half scale f in = 1khz noise bw = 22khz figure 33. thd + n vs. amplitude 0.0010 0.0005 0 ?0.0015 ?0.0005 ?0.0010 0 ?10 10 20 30 40 50 60 time (s) voltage (v) 08076-046 v dd /v ss = 5v/0v i aw = 200a code = half scale figure 34. digital feedthrough 70 60 50 40 0 30 20 10 ?40 ?20 0 20 40 60 80 100 120 temperature (c) 08076-020 number of codes (ad5274) number of codes (ad5272) 15.0 15.5 12.5 10.0 7.5 5.0 2.5 0 v dd /v ss = 5v/0v 20k ? 50k ? 100k ? figure 35. maximum code loss vs. power supply range
ad5272/ad5274 rev. c | page 16 of 28 4 5 6 7 8 voltage (v) time (seconds) 0.07 0.09 0.11 0.13 0.15 0.17 0 8076-029 figure 36. v ext_cap waveform while writing fuse 0.006 ?0.002 ?0.001 0 0.001 0.002 0.003 0.004 0.005 0 1000900800700 600500400 300200100 ? r aw resistance (%) operation at 150c (hours) 08076-038 v dd /v ss = 5v/0v i aw = 10a code = half scale figure 37. long-term drift accelerated average by burn-in
ad5272/ad5274 rev. c | page 17 of 28 v ms i w test circuits figure 38 to figure 42 define the test conditions used in the specifications section. a w dut 08076-033 r wa = figure 38. resistor position nonlinearity error (rheostat operation; r-inl, r-dnl) v ms i w r w = r wa 2 a w i w dut v ms code = 0x00 08076-034 v dd i w v ms figure 39. wiper resistance a w v+ ? v ms % ? v dd % v ms v dd v + = v dd 10 % psrr (db) = 20 log pss (%/%) = 08076-035 v ms figure 40. power supply sensitivity (pss, psrr) a w dut v 1g ? 08076-036 figure 41. gain vs. frequency i cm dut w a nc = no connect gnd +2.75v nc +2.75v ?2.75v ?2.75v gnd gnd 08076-037 figure 42. common leakage current
ad5272/ad5274 rev. c | page 18 of 28 theory of operation the ad5272 and ad5274 digital rheostats are designed to operate as true variable resistors for analog signals within the terminal voltage range of v ss < v term < v dd . the rdac register contents determine the resistor wiper position. the rdac register acts as a scratchpad register, which allows unlimited changes of resistance settings. the rdac register can be programmed with any position setting using the i 2 c interface. when a desirable wiper position is found, this value can be stored in a 50-tp memory register. thereafter, the wiper position is always restored to that position for subsequent power-up. the storing of 50-tp data takes approximately 350 ms; during this time, the ad5272/ad5274 is locked and does not acknowledge any new command thereby preventing any changes from taking place. the acknowledge bit can be polled to verify that the fuse program command is complete. the ad5272/ad5274 also feature a patented 1% end-to-end resistor tolerance. this simplifies precision, rheostat mode, and open-loop applications where knowledge of absolute resistance is critical. serial data interface the ad5272/ad5274 have 2-wire i 2 c-compatible serial inter- faces. each of these devices can be connected to an i 2 c bus as a slave device under the control of a master device; see figure 3 for a timing diagram of a typical write sequence. the ad5272/ad5274 support standard (100 khz) and fast (400 khz) data transfer modes. support is not provided for 10-bit addressing and general call addressing. the ad5272/ad5274 each has a 7-bit slave address. the five msbs are 01011 and the two lsbs are determined by the state of the addr pin. the facility to make hardwired changes to addr allows the user to incorporate up to three of these devices on one bus as outlined in table 11 . the 2-wire serial bus protocol operates as follows: the master initiates a data transfer by establishing a start condition, which is when a high-to-low transition on the sda line occurs while scl is high. the next byte is the address byte, which consists of the 7-bit slave address and a r/ w bit. the slave device cor- responding to the transmitted address responds by pulling sda low during the ninth clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its shift register. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl. when all data bits have been read or written, a stop condition is established. in write mode, the master pulls the sda line high during the 10th clock pulse to establish a stop condition. in read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the sda line remains high). the master then brings the sda line low before the 10th clock pulse, and then high during the 10th clock pulse to establish a stop condition. shift register for the ad5272/ad5274, the shift register is 16 bits wide, as shown in figure 2 . the 16-bit word consists of two unused bits, which should be set to zero, followed by four control bits and 10 rdac data bits (note that for the ad5274 only, the lower two rdac data bits are dont care if the rdac register is read from or written to), and data is loaded msb first (bit 15). the four control bits determine the function of the software command ( tabl e 12 ). figure 43 shows a timing diagram of a typical ad5272/ad5274 write sequence. the command bits (cx) control the operation of the digital potentiometer and the internal 50-tp memory. the data bits (dx) are the values that are loaded into the decoded register. table 11. device address selection addr a1 a0 7-bit i 2 c device address gnd 1 1 0101111 v dd 0 0 0101100 nc (no connection) 1 1 0 0101110 1 not available in bipolar mode. v ss < 0 v.
ad5272/ad5274 rev. c | page 19 of 28 write operation it is possible to write data for the rdac register or the control register. when writing to the ad5272/ad5274, the user must begin with a start command followed by an address byte (r/ w = 0), after which the ad5272/ad5274 acknowledges that it is prepared to receive data by pulling sda low. two bytes of data are then written to the rdac, the most significant byte followed by the least significant byte; both of these data bytes are acknowledged by the ad5272/ad5274. a stop condition follows. the write operations for the ad5272/ ad5274 are shown in figure 43 . a repeated write function gives the user flexibility to update the device a number of times after addressing the part only once, as shown in figure 44 . scl sda start by master ack. by ad5272/ad5274 frame 1 serial bus address byte frame 2 most significant data byte frame 3 least significant data byte scl (continued) sda (continued) ack. by ad5272/ad5274 ack. by ad5272/ad5274 stop by master 0 19 1 99 9 1 1 011a1a0 00c3c2 c1 c0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 r/w 0 8076-005 figure 43. write command 0 8076-006 scl sda start by master frame 2 most significant data byte frame 1 serial bus address byte 0 19 1 99 9 1 1 0 1 1 a1 a0 r/w 0 0 c3 c2 c1 c0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 scl (continued) sda (continued) frame 3 least significant data byte scl (continued) sda (continued) stop by master 1 99 d7 d6 d5 d4 d3 d2 d1 d0 (continued) (continued) frame 5 least significant data byte 1 99 0 0 c3c2c1c0d9d8 frame 4 most significant data byte scl sda ack. by ad5272 2/ad5274 ack. by ad5272 2/ad5274 ack. by ad5272 2/ad5274 ack. by ad5272 2/ad5274 ack. by ad5272 2/ad5274 figure 44. multiple write
ad5272/ad5274 rev. c | page 20 of 28 read operation when reading data back from the ad5272/ad5274, the user must first issue a readback command to the device, this begins with a start command followed by an address byte (r/ w = 0), after which the ad5272/ad5274 acknowledges that it is prepared to receive data by pulling sda low. two bytes of data are then written to the ad5272/ad5274, the most significant byte followed by the least significant byte; both of these data bytes are acknowledged by the ad5272/ad5274. a stop condition follows. these bytes contain the read instruc- tion, which enables readback of the rdac register, 50-tp memory, or the control register. the user can then read back the data beginning with a start command followed by an address byte (r/ w = 1), after which the device acknowledges that it is prepared to transmit data by pulling sda low. two bytes of data are then read from the device, as shown in . a stop condition follows. if the master does not acknowledge the first byte, the second byte is not transmitted by the ad5272/ad5274. figure 45 0 19 1 99 9 1 1 0 1 1 a1 a0 r/w 0 0 c3 c2 c1 c0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 19 1 99 9 1 1 0 1 1 a1 a0 r/w 0 0 x x x x d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ack. by ad5272/ad5274 ack. by ad5272/ad5274 ack. by ad5272/ad5274 ack. by ad5272/ad5274 ack. by master no ack. by master 08076-007 scl sd a scl (continued) sda (continued) scl (continued) sda (continued) start by master scl sd a start by master stop by master stop by master frame 1 serial bus address byte frame 1 serial bus address byte frame 2 most significant data byte frame 2 most significant data byte frame 3 least significant data byte frame 3 least significant data byte figure 45. read command
ad5272/ad5274 rev. c | page 21 of 28 rdac register the rdac register directly controls the position of the digital rheostat wiper. for example, when the rdac register is loaded with all zeros, the wiper is connected to terminal a of the variable resistor. it is possible to both write to and read from the rdac register using the i 2 c interface. the rdac register is a standard logic register; there is no restriction on the number of changes allowed. 50-tp memory block the ad5272/ad5274 contain an array of 50-tp programmable memory registers, which allow the wiper position to be pro- grammed up to 50 times. table 16 shows the memory map. command 3 in table 12 programs the contents of the rdac register to memory. the first address to be programmed is location 0x01, see tabl e 16 , and the ad5272/ad5274 incre- ments the 50-tp memory address for each subsequent program until the memory is full. programming data to 50-tp consumes approximately 4 ma for 55 ms, and takes approximately 350 ms to complete, during which time the shift register is locked pre- venting any changes from taking place. bit c3 of the control register in table 15 can be polled to verify that the fuse program command was successful. no change in supply voltage is required to program the 50-tp memory; however, a 1 f capacitor on the ext_cap pin is required as shown in figure 47 . prior to 50-tp activation, the ad5272/ad5274 is preset to midscale on power-up. it is possible to read back the contents of any of the 50-tp memory registers through the i 2 c interface by using command 5 in table 1 2 . the lower six lsb bits, d0 to d5 of the data byte, select which memory location is to be read back. a binary encoded version address of the most recently programmed wiper memory location can be read back using command 6 in table 12 . this can be used to monitor the spare memory status of the 50-tp memory block. write protection on power-up, serial data input register write commands for both the rdac register and the 50-tp memory registers are disabled. the rdac write protect bit (bit c1) of the control register (see table 14 and table 15 ) is set to 0 by default. this disables any change of the rdac register content regardless of the software commands, except that the rdac register can be refreshed from the 50-tp memory using the software reset, command 4, or through hardware by the reset pin. to enable programming of the variable resistor wiper position (programming the rdac register), the write protect bit (bit c1) of the control register must first be programmed. this is accomplished by loading the serial data input register with command 7 (see ). to enable programming of the 50-tp memory block, bit c0 of the control register, which is set to 0 by default, must first be set to 1. table 12 table 12. command operation truth table command[db13:db10] data[db9:b0] 1 command number c3 c2 c1 c0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 operation 0 0 0 0 0 x x x x x x x x x x nop: do nothing. 1 0 0 0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 2 d0 2 write contents of serial register data to rdac. 2 0 0 1 0 x x x x x x x x x x read contents of rdac wiper register. 3 0 0 1 1 x x x x x x x x x x store wiper setting: store rdac setting to 50-tp. 4 0 1 0 0 x x x x x x x x x x software reset: refresh rdac with the last 50-tp memory stored value. 5 3 0 1 0 1 x x x x d5 d4 d3 d2 d1 d0 read contents of 50-tp from the sdo output in the next frame. 6 0 1 1 0 x x x x x x x x x x read address of the last 50-tp programmed memory location. 7 4 0 1 1 1 x x x x x x x d2 d1 d0 write contents of the serial register data to the control register. 8 1 0 0 0 x x x x x x x x x x read contents of the control register. 9 1 0 0 1 x x x x x x x x x d0 software shutdown. d0 = 0; normal mode. d0 = 1; shutdown mode. 1 x = dont care. 2 ad5274 = dont care. 3 see table 16 for the 50-tp memory map. 4 see table 15 fo r bit details.
ad5272/ad5274 rev. c | page 22 of 28 table 13. write and read to rdac and 50-tp memory din sdo 1 action 0x1c03 0xxxxx enable update of wiper position and 50-tp memory contents through digital interface. 0x0500 0x1c03 write 0x100 to the rdac register, wiper moves to ? full-scale position. 0x0800 0x0500 prepare data read from rdac register. 0x0c00 0x100 stores rdac register content into 50-tp memory. 16-bit wo rd appears out of sdo, where last 10-bits contain the contents of the rdac register 0x100. 0x1800 0x0c00 prepare data read of last programmed 50-tp memory monitor location. 0x0000 0xxx19 nop instruction 0 sends a 16-bit word out of sdo, where the si x lsbs last 6-bits contain the binary address of the last programmed 50-tp memory location, for example, 0x19 (see table 16 ). 0x1419 0x0000 prepares data read from memory location 0x19. 0x2000 0x0100 prepare data read from the control register. sends a 16-bit word out of sdo, where the last 10-bits contain the contents of memory location 0x19. 0x0000 0xxxxx nop instruction 0 sends a 16-bit word out of sdo, where the la st four bits contain the contents of the control register. if bit c3 = 1, fuse program command successful. 1 x is dont care. table 14. control register bit map db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 c3 c2 c1 c0 table 15. control register description bit name description c0 50-tp program enable 0 = 50-tp program disabled (default) 1 = enable device for 50-tp program c1 rdac register write protect 0 = wiper position frozen to value in 50-tp memory (default) 1 1 = allow update of wiper position through a digital interface c2 resistor performance enable 0 = rdac resistor tolerance calibration enabled (default) 1 = rdac resistor tolerance calibration disabled c3 50-tp memory program success bit 0 = fuse program command unsuccessful (default) 1 = fuse program command successful 1 wiper position is frozen to the last va lue programmed in the 50-tp me mory. wiper freezes to midscal e if 50-tp memory has not b een previously programmed. table 16. memory map data byte [db9:db8] 1 command number d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 register contents x x x 0 0 0 0 0 0 0 reserved x x x 0 0 0 0 0 0 1 1st programmed wiper location (0x01) x x x 0 0 0 0 0 1 0 2nd programmed wiper location (0x02) x x x 0 0 0 0 0 1 1 3rd programmed wiper location (0x03) x x x 0 0 0 0 1 0 0 4th programmed wiper location (0x04) x x x 0 0 0 1 0 1 0 10th programmed wiper location (0xa) x x x 0 0 1 0 1 0 0 20th programmed wiper location (0x14) x x x 0 0 1 1 1 1 0 30th programmed wiper location (0x1e) x x x 0 1 0 1 0 0 0 40th programmed wiper location (0x28) 5 x x x 0 1 1 0 0 1 0 50th programmed wiper location (0x32) 1 x is dont care.
ad5272/ad5274 rev. c | page 23 of 28 50-tp memory write-acknowledge polling after each write operation to the 50-tp registers, an internal write cycle begins. the i 2 c interface of the device is disabled. to determine if the internal write cycle is complete and the i 2 c interface is enabled, interface polling can be executed. i 2 c interface polling can be conducted by sending a start condition, followed by the slave address and the write bit. if the i 2 c interface responds with an acknowledge (ack), the write cycle is complete and the interface is ready to proceed with further operations. otherwise, i 2 c interface polling can be repeated until it completes. reset the ad5272/ad5274 can be reset through software by executing command 4 (see table 12 ) or through hardware on the low pulse of the reset pin. the reset command loads the rdac register with the contents of the most recently programmed 50-tp memory location. the rdac register loads with midscale if no 50-tp memory location has been previously programmed. tie reset to v dd if the reset pin is not used. resistor performance mode this mode activates a new, patented 1% end-to-end resistor tolerance that ensures a 1% resistor tolerance on each code, that is, code = half scale and r wa = 10 k 100 . see table 2 , table 3 , table 5 , and table 6 to check which codes achieve 1% resistor tolerance. the resistor performance mode is activated by programming bit c2 of the control register (see table 14 and table 15 ). shutdown mode the ad5272/ad5274 can be shut down by executing the software shutdown command, command 9 (see table 12 ), and setting the lsb to 1. this feature places the rdac in a zero-power- consumption state where terminal ax is disconnected from the wiper terminal. it is possible to execute any command from table 12 while the ad5272 or ad5274 is in shutdown mode. the part can be taken out of shutdown mode by executing command 9 and setting the lsb to 0, or by issuing a software or hardware reset. rdac architecture to achieve optimum performance, analog devices has patented the rdac segmentation architecture for all the digital potentiometers. in particular, the ad5272/ad5274 employ a three-stage segmentation approach, as shown in figure 46 . the ad5272/ ad5274 wiper switch is designed with the transmission gate cmos topology. a w 10-/8-bit address decoder r l r l r m r m r w s w r w 08076-008 figure 46. simplified rdac circuit programming the variable resistor rheostat operation1% resistor tolerance the nominal resistance between terminal w and terminal a, r wa , is available in 20 k, 50 k, and 100 k, and 1024-/256-tap points accessed by the wiper terminal. the 10-/8-bit data in the rdac latch is decoded to select one of the 1024 or 256 possible wiper settings. the ad5272/ ad 5274 contain an internal 1% resistor tolerance calibration feature which can be disabled or enabled, enabled by default, or by programming bit c2 of the control register (see table 15 ). the digitally programmed output resis- tance between the w terminal and the a terminal, r wa , is calibrated to give a maximum of 1% absolute resistance error over both the full supply and temperature ranges. as a result, the general equations for determining the digitally programmed output resistance between the w terminal and a terminal are as follows: for the ad5272 wa wa r d dr = 1024 )( (1) for the ad5274 wa wa r d dr = 256 )( (2) where: d is the decimal equivalent of the binary code loaded in the 10-/8-bit rdac register. r wa is the end-to-end resistance. in the zero-scale condition, a finite total wiper resistance of 120 is present. regardless of which setting the part is oper- ating in, take care to limit the current between the a terminal to b terminal, w terminal to a terminal, and w terminal to b terminal, to the maximum continuous current of 3 ma, or the pulse current specified in tabl e 8 . otherwise, degradation or possible destruction of the internal switch contact can occur.
ad5272/ad5274 rev. c | page 24 of 28 the ground pins of the ad5272/ad5274 devices are primarily used as digital ground references. to minimize the digital ground bounce, join the ad5272/ad5274 ground terminal remotely to the common ground. the digital input control signals to the ad5272/ad5274 must be referenced to the device ground pin (gnd) and satisfy the logic level defined in the specifications section. an internal level shift circuit ensures that the common-mode voltage range of the three terminals extends from v ss to v dd , regardless of the digital input level. ext_cap capacitor a 1 f capacitor to v ss must be connected to the ext_cap pin (see figure 47 ) on power-up and throughout the operation of the ad5272/ad5274. ad5272/ ad5274 50_otp memory block ext_cap c1 1f v ss v ss 08076-009 power-up sequence because there are diodes to limit the voltage compliance at ter mina l a and ter mina l w ( s e e figure 48 ), it is important to power v dd /v ss first before applying any voltage to terminal a and terminal w; otherwise, the diode is forward-biased such that v dd /v ss are powered unintentionally. the ideal power-up sequence is v ss , gnd, v dd , digital inputs, v a , and v w . the order of powering v a , v w , and digital inputs is not important as long as they are powered after v dd /v ss . figure 47. ext_cap hardware setup terminal voltage operating range the positive v dd and negative v ss power supplies of the ad5272/ad5274 define the boundary conditions for proper 2-terminal digital resistor operation. supply signals present on ter mina l a and ter mina l w t h at exce e d v dd or v ss are clamped by the internal forward-biased diodes (see figure 48 ). as soon as v dd is powered, the power-on preset activates, which first sets the rdac to midscale and then restores the last programmed 50-tp value to the rdac register. v ss v dd a w 08076-109 figure 48. maximum terminal voltages set by v dd and v ss
ad5272/ad5274 rev. c | page 25 of 28 outline dimensions compliant to jedec standards mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 10 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 coplanarity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 49. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters 2.48 2.38 2.23 0.50 0.40 0.30 121009-a top view 10 1 6 5 0.30 0.25 0.20 bottom view pin 1 index area seating plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed pad 3.10 3.00 sq 2.90 p i n 1 i n d i c a t o r ( r 0 . 1 5 ) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 50. 10-lead frame chip scale package [lfcsp_wd] 3 mm 3mm body, very thin, dual lead (cp-10-9) dimensions shown in millimeters
ad5272/ad5274 rev. c | page 26 of 28 ordering guide model 1 r aw (k) resolution temperature range packag e description package option branding ad5272brmz-20 20 1,024 ?40c to +125c 10-lead msop rm-10 de6 ad5272brmz-20-rl7 20 1,024 ?40c to +125c 10-lead msop rm-10 de6 ad5272brmz-50 50 1,024 ?40c to +125c 10-lead msop rm-10 de7 ad5272brmz-50-rl7 50 1,024 ?40c to +125c 10-lead msop rm-10 de7 ad5272brmz-100 100 1,024 ?40c to +125c 10-lead msop rm-10 de5 ad5272brmz-100-rl7 100 1,024 ?40c to +125c 10-lead msop rm-10 de5 ad5272bcpz-20-rl7 20 1,024 ?40c to +125c 10-lead lfcsp_wd cp-10-9 de4 ad5272bcpz-100-rl7 100 1,024 ?40c to +125c 10-lead lfcsp_wd cp-10-9 de3 ad5274brmz-20 20 256 ?40c to +125c 10-lead msop rm-10 dee AD5274BRMZ-20-RL7 20 256 ?40c to +125c 10-lead msop rm-10 dee ad5274brmz-100 100 256 ?40c to +125c 10-lead msop rm-10 ded ad5274brmz-100-rl7 100 256 ?40c to +125c 10-lead msop rm-10 ded ad5274bcpz-20-rl7 20 256 ?40c to +125c 10-lead lfcsp_wd cp-10-9 de9 ad5274bcpz-100-rl7 100 256 ?40c to +125c 10-lead lfcsp_wd cp-10-9 de8 eval-ad5272sdz evaluation board 1 z = rohs compliant part.
ad5272/ad5274 rev. c | page 27 of 28 notes
ad5272/ad5274 rev. c | page 28 of 28 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ?2009C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08076-0-11/10(c)

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